1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an IC tester that adjusts timing of test events following an asynchronous trigger signal edge so that subsequent test events occur with predictable delays following the trigger signal edge.
2. Description of Related Art
An integrated circuit (IC) tester typically organizes an IC test into a succession of test cycles. A pattern generator within the tester produces a control data word (a xe2x80x9cvectorxe2x80x9d) before the start of each test cycle referencing any test activities to be carried out during the following test cycle. Test activities may include, for example changing a state of a test signal input to an IC terminal or sampling an output signal produced at a DUT terminal. When the timing of test activities is controlled with a higher resolution than the period of one test cycle, the vector also indicates a time during the test cycle at which the tester is to initiate the referenced test activity.
The sequence of vectors that control test activities during a test may be supplied to the tester before the test either directly or in the form of an algorithmic program for generating the vector sequence. In either case, the vector sequence completely predetermines the course of the test, including the test activities to be carried out and the times during each test cycle at which each test activity is to be carried out. The start of each test cycle is controlled by a period clock signal derived from a master clock signal produced by a stable oscillator, and the vectors reference the timing of all test events to edges of the period clock signal. However it would be beneficial in some applications if a tester could time its test activities in relation to an edge of externally generated trigger signal edge which may or may not coincide with an edge of the period clock signal. For example we might want a tester to synchronize the timing of its test activities to a trigger signal produced by external instrumentation that is to carry out test activities concurrently with the tester. Or we may want a tester to re-synchronize its test activities to a trigger signal produced during a test, for example, by the IC under test itself.
Suppose, for example, we want to test an asynchronous IC that produces an output handshaking signal at one of its terminals indicating when output data is available at one or more of its terminals. Suppose also that would like a tester to be able to sample that output data with some defined delay following an edge of that handshaking signal. In a conventional tester, vectors define event timing with respect to edges of the period clock. Thus when a handshaking signal edge does not occur with a predictable delay following an edge of the period clock, we cannot program a tester to respond to the handshaking signal with a predictable delay.
What is needed is an integrated circuit tester that can adjust the timing of test events defined by a vector sequence following an asynchronous trigger signal edge so that each test event occurs with predictable delay following the trigger signal edge.
A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles and a vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T0 through T(Nxe2x88x921), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T0 signal, and each vector referencing a test event also indicates a time delay following the nominal start of the test cycle at which the event is to occur by referencing one of the timing signals T0 through T(Nxe2x88x921).
In accordance with one aspect of the invention, whenever the tester receives an input trigger signal edge, the tester determines an offset between the most recent T0 signal edge and the occurrence of the trigger signal edge. During all test cycles thereafter, the tester delays test events from the nominal time defined by the vectors by the amount of the offset. In doing so, the tester makes the delay of each subsequent test event with respect to the trigger signal edge a predictable function of the vector sequence.
It is accordingly an object of the invention to provide an integrated circuit tester that can adjust the timing of each test event defined by a vector sequence following a trigger signal edge so that subsequent test events occur with predictable delays following the trigger signal edge.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.